Back-End/Physical Design
Επίδραση του BE στη σχεδίαση ενός chip
Chip Design Walkthrough (traditional)
Back-End Overview
PPT Slide
Floorplanning
Floorplanning Design Flow
Flat Flow with Clock-Tree Synthesis
Cell3 Ensemble
Hierarchical Design Flows
Preview top-down floor-planning phase
Cell3 Ensemble (2)
In-Place-Optimization (IPO)
DRC/ERC/LVS Verification
Dracula Applications
LVS Philosophy
Synopsys Flow (1)
Synopsys : Chip Architect Flow
Email: kornaros@ics.forth.gr