Flat Flow with Clock-Tree Synthesis

Synopsys Synthesis

Preview Floorplan

C3 Placement

C3 CTS

C3 Routing

C3 Extract

Synopsys Delay Calc

Early Delay Calc

CTS Delays Collapse

Synopsys TA

(with dummy buffer)

Verilog Simulation

(with dummy buffer)

Synopsys IPO

CTS reinsertion

C3 Placement ECO

C3 Routing ECO

PRE LAYOUT

LAYOUT

POST LAYOUT

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