LVS Philosophy

A

A

Z

Z

gnd!

vdd!

Check if transistors, interconnections in the layout match schematic nets and devices.

HDL (Verilog) gate level netlist

module top ( Out, In ) ;

supply0 gnd ;

supply1 vdd ;

input In ;

output Out ;

wire net1 ;

IV I1 ( . Z(net1), .A(In) ) ;

IV I2 ( . Z(Out), .A(net1) ) ;

endmodule

CDL transistor level netlist

.subckt IV Z A

MN1 Z A gnd gnd N w=1.60u l=0.35u ad=1.56e-12 as=1.56e-12 pd=3.55e-06

MP1 Z A vdd vdd P w=2.40u l=0.35u ad=2.34e-12 as=2.34e-12 pd=4.3e-06

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