3.3 Clock Domains and Elastic Buffers (U.Crete, CS-534)

CS-534: Packet Switch Architecture
Spring 2003

Department of Computer Science
© University of Crete, Greece

3.3 Clock Domains and Elastic Buffers

[Up: Table of Contents]
[Prev: 3.2 Off-Chip Memories]

[Next: 3.4 Multi-Queue Structures]

Communicating across Clock Domains

The need for cross-clock-domain communication

Reference: W. Dally, J. Poulton: "Digital Systems Engineering", Cambridge University Press, 1998, ISBN 0-521-59292-5 (section 10.2: Synchronization Fundamentals).

Was the signal sampled before or after its change?

Asynchronous sampling of multibit signals (almost impossible)

Elastic Buffer (2-asynchronous-port SRAM)

Reminder: Circular Array Implementation of FIFO Queue

One-Hot Pointer Encoding

Empty/Full FIFO Detection using One-Hot Pointer Encoding

Empty and Full flags: asynchronous to either clock

Synchronized Empty/Full Generation for High-Throughput Operation

Synchronized Empty/Full Generation: explanations

Reference: W. Dally, J. Poulton: "Digital Systems Engineering", Cambridge University Press, 1998, ISBN 0-521-59292-5 (section 10.3: Synchronizer Design, especially section 10.3.4.2).

[Up: Table of Contents]
[Prev: 3.2 Off-Chip Memories]

[Next: 3.4 Multi-Queue Structures]

Up to the Home Page of CS-534