Short Notes on QDR Memories - Answer to a Question:

Question:
What is the relation between burst size and access (address) rate in QDR SRAM's?

Answer:
Let us call "burst time" the duration of one write-burst's data on the
D bus, which equals the duration of one read-burst's data on the Q bus.

Due to DDR timing on the D and Q buses, the burst time is:
* For burst-of-4, it is 4 half-cycles = 2 clock cycles;
* For burst-of-2, it is 2 half-cycles = 1 clock cycle.

Each burst consists of *consecutive* data words, hence a single address
is needed and suffices for the access to this burst.
During each burst time, the Address bus must supply *both* the
write-address for the write-burst and the read-address for the read-burst.
Hence, in the case of burst-of-2, as in slide 19, the address bus
must supply 2 addresses in every 1 clock cycle (=1 burst time),
i.e. it must use DDR timing.
In the case of burst-of-4, as in slide 20, the address bus
must supply 2 addresses in every 2 clock cycles (=1 burst time),
thus it can use simple (non DDR) timing.

Thus, for an given fixed clock frequency, the address throughput
(which equals the sum of the "independent write" (50%) plus
"independent read" (the other 50%) access rate), is twice larger
in burst-of-2 devices, than it is in burst-of-4 devices:
Increasing the burst size is equivalent to increasing the access width,
which is an easy way to increase the data throughput under a given fixed
access rate, or to decrease the access rate under a given fixed
data throughput....

7 March 2011,
M. Katevenis.