Nikolaos Chrysos
Collaborating Researcher at ICS-FORTH
Computer Architecture and VLSI Systems (CARV) Laboratory
Visiting Instructor
Computer Science Department of University of Crete

Email: nchrysos at ics dot forth dot gr
Telephone: +30 2811 391406
Postal address: FORTH-ICS, 100 Plastira, Vassilika Vouton, Heraklion, Crete, GR-70013, Greece.

Short biography
Nikolaos Chrysos received his PhD in Computer Science from the University of Crete in 2007 on congestion control for multi-stage fabrics, which earned him an IBM Phd Fellowship. Between 2007 and 2008, he was a Visiting Instructor at the Electronics and Computer Engineering Department of the Technical University of Crete, and a Postdoctoral Fellow at ICS-FORTH. From 2009 to 2014, he was a Visiting Scientist at IBM Research--Zurich, where he contributed to the design and the implementation of a high-performance server-rack fabric for 100G Ethernet. While with IBM, N. Chrysos also co-led the design of a switch chip supporting 136 ports at 25 Gb/s, and participated in the HISTORIC EU-funded research project on all-optical networks. Since October 2014, he is with ICS-FORTH, working on high-speed datacenter networks, microservers and low-power systems. Dr. Chrysos has many peer-reviewed publications in top conferences and journals, is the (co-)inventor of seven granted patents, and a recipient of four IBM Patent Plateau Awards. He is a member of HiPEAC and of ACM.

Research interests

  • interconnection networks & switching fabrics
  • computer/server architecture, datacenters, high-performance computers
  • microservers
  • congestion control and routing
  • IO network stack
  • high-radix switches
  • virtualization
  • on-chip networks


  • IBM PhD Fellowship in 2004-2005 and 2005-2006 external link
  • Four IBM Patent plateau awards -- A plateau is awarded for filing four (4) patent applications
  • High value patent applicaton (IBM)
  • HiPEAC Paper Award, 2015

    News: HiPEAC Thematic Session on System-level Interconnects, held at Milano, Sept. 2015

    Current Projects

  • European Exascale Processor-Memory Node Design (FETHPC-1-2014) ExaNoDe will investigate, develop and pilot (technology readiness level 7) a highly efficient, highly integrated, multi-way, high-performance, heterogeneous compute element aimed towards exascale computing and demonstrated using hardware-emulated interconnect. It will build on multiple European initiatives for scalable computing, utilizing low-power processors and advanced nanotechnologies.
  • European Exascale Interconnects and Storage (FETHPC-1-2014) logo ExaNeSt will develop, evaluate, and prototype the physical platform and architectural solution for a unified Communication and Storage Interconnect and the physical rack and environmental structures required to deliver European Exascale Systems. The consortium brings technology, skills, and knowledge across the entire value chain from computing IP to packaging and system deployment; and from operating systems, storage, and communication to HPC with big data management, algorithms, applications.

    Past Projects

  • Server-rack fabrics running at 100G
  • Clos on-chip networks & multi-terabit switching chips
  • Heterogeneous InP on Silicon Technology for Optical Routing and LogIC (HISTORIC)
  • Switching fabrics with small internal buffers for scalable non-blocking interconnects
  • Buffered crossbar switches


  • Packet Switch Architecture, Spring 2015, Computer Science Department, University of Crete
  • Logic design, Autumn 2008, 2009, ECE Department, Technical University of Crete
  • Recent publications

    M. Katevenis, N. Chrysos, M. Marazakis et al. "The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems", to appear in Proceedings of Euromicro Conference on Digital System Design (DSD), Aug. 31 - Sept. 2, Limassol, Cyprus paper
    A. Psathakis, V. Papaefstathiou, N. Chrysos, F. Chaix, V. Vassilakis, D. Pnevmatikatos, M. Katevenis"A Systematic Evaluation of Emerging Mesh-like CMP NoCs", IEEE/ACM Symposium on Architectures for Networking and Communications Systems (ANCS), CA, May 2015
    N. Chrysos, F. Neeser, M. Gusat, C. Minkenberg, W. Denzel, C. Basso, M. Rudquist, K. Valk, B. Vanderpool "Large Switches or Blocking Multi-Stage Networks? An Evaluation of Routing Strategies for Datacenter Fabrics", Computer Networks, Elsevier, to appear
    N. Chrysos, F. Neeser, R. Clauberg, D. Crisan, K. Valk, C. Basso, C. Minkenberg, M. Gusat, "Unbiased QCN for Scalable Server-Rack Fabrics", IEEE Micro, to appear paper
    N. Chrysos, C. Minkenberg, M. Rudquist, C. Basso, B Vanderpool, "SCOC: High-Radix Crossbars Made Of Bufferless Clos Networks", IEEE Symposium on High Performance Computer Architecture (HPCA), CA, Feb. 2015 paper
    N. Chrysos, F. Neeser, B. Vanderpool, M. Rudquist, K. Valk, T. Greenfield, C. Basso, "Integration and QoS of Multicast Traffic in a Server-Rack Fabric with 640 100G Ports", IEEE/ACM Symposium on Architectures for Networking and Communications Systems (ANCS), Los Angeles, Oct. 2014 paper
    D. Crisan, R. Birke, N. Chrysos, C. Minkenberg, M. Gusat, "zFabric: How to Virtualize Lossless Ethernet", IEEE International Conference on Cluster Computing (CLUSTER), Madrid, Spain, Sept. 2014


  • Publications
  • Patents
  • Invited talks
  • Professional activities