DIONISIOS N. PNEVMATIKATOS pnevmati ** at ** ics . forth . gr,     pnevmati ** at ** ece . tuc . gr

Affiliated Researcher Computer Architecture and VLSI Systems Lab (CARV) Institute of Computer Science (ICS) Foundation for Research and Technology -- Hellas (FORTH) ICS, FORTH, Science & Technology Park of Crete, Nikolaou Plastira 100, Vassilika Vouton, P.O. Box 1385, Heraklion, Crete, GR 70013, Greece Tel: +30 (2810) 39 16 57 FAX: 39 16 61

Professor, Director Microprocessor and Hardware Laboratory (MHL) Electronic and Computer Engineering Department Technical University of Crete (TUC) ECE Department, Technical University of Crete, Kounoupidiana Campus, Chania, Crete, GR 731 00, Greece Tel: +30 (28210) 37 344 FAX: 37 542 Home Tel: +30 (28210) 33 813

Research Interests:

His research interests are in the broader area of Computer Architecture:

• Design and Implementation of High-Performance and Cost-Effective Systems
• Reconfigurable Computing
• Application Acceleration
• Reliable System Design
• Custom and Application-Specific Architectures
• Hardware Acceleration of Bioinformatics Algorithms

Participation in Research Projects:

• FASTER – Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration, ICT STREP, Coordinator
• DeSyRe – on-Demand System Reliability, ICT STREP, Scientific Coordinator on behalf of the CARV Laboratory
• Encore – ENabling technologies for a programmable many-CORE, ICT STREP (member)
• SARC – Scalable computer ARChitecture, ICT Integrated Project aiming to develop a scalable integrated architecture applicable to a wide range of applications (member).
• HiPEAC – European Network of Excellence on High Performance and Embedded Architecture and Compilation, ICT Network of Excellence, Member of the Interconnects and Reconfigurable Computing Clusters (member)
• VPLANET - Advanced Verification and Emulation Platform, GSRT, Scientific Coordinator
• EASY/HIPERLAN - Advanced Pipelining and Implementation of a HIPERLAN Wireless Modem
• PRO3 – Architecture, Design and Implementation of the I/O Subsystem of a Network Processor
• PENED 1999 PLATO - A Development Platform for Protocol Boosting in ATM networks (GSRT, graded 9.9/10)
• ASSICOM – Design and Implementation of the ATLAS I ATM single chip switch (member)
• SPEAR-II – Superscalar Network Processor Architecture (member)

Short CV:

Dionisios Pnevmatikatos is a Professor and former Chair of the Electronic and Computing Engineering Department, Technical University of Crete and a Researcher at the Computer Architecture and VLSI Systems (CARV) Laboratory of the Institute of Computer Science, FORTH in Greece. He received his B.Sc. degree in Computer Science from the Department of Computer Science, University of Crete in 1989 and M.Sc. and Ph.D. degrees in Computer Science from the Department of Computer Science, University of Wisconsin-Madison in 1991 and 1995 respectively. His research interests are in the broader area of Computer Architecture, where he investigates the Design and Implementation of High-Performance and Cost-Effective Systems, Reliable System Design, and Reconfigurable Computing. Within this context, he has performed research in Networking Hardware and Network Processors, Application Acceleration, Custom and Application-Specific Architectures, and Hardware Acceleration of Bioinformatics Algorithms. He has published several articles in international conferences and journals and has served on the program committees of numerous international conferences. He is the Program Co-Chair of the 21st International Conference on Field Programmable Logic and Applications (FPL), and was the Chair and Vice-Chair in the Architecture and Microarechitecture Track of the Design and Test Europe (DATE) conference in years 2007-2010. He was the General Co-Chair of the 2008 Panhellenic Conference on Informatics (PCI) and of the International Workshop on Rapid System Prototyping (RSP) in 2007, and has been a member of the Technical Program Committee in many of the key international conferences of his field. He is currently the Coordinator of the FASTER project (ICT, STREP) and has participated in numerous national and European projects. He is a member of IEEE.

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Publications List

Teaching:

At the ECE Department, Technical University of Crete:

• Advanced Computer Architecture
• Computer Architecture
• Computer Organization
• Digital Computers
• Advanced Logic Design
• Logic design
• Parallel and Ddistributed Computer Architectures

At Department of Computer Science, University of Crete:

• HY 225: Computer Organization, Spring 2000
• HY 527: Parallel Computer Architecture, Spring 1999
• HY 425: Computer Architecture, Fall 1998
• HY 625: Advanced Computer Architecture, Fall 1997

Education:

• Ph.D. Computer Science, University of Wisconsin-Madison , December 1995. Advisor: Guri Sohi
  Thesis: ``Incorporating Guarded Execution in Existing Instruction Sets''.
• M.S. Computer Science, University of Wisconsin-Madison , 1991
• B.S. Computer Science, University of Crete, Greece , 1989

While I studied in the Department of Computer Sciences of the University of Wisconsin-Madison, I was a member of the Multiscalar and the Computer Architecture and VLSI groups.

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