Greek State Fellowship for ranking first in his class, 1973 - 1978,
as undergraduate student at NTUA.
1.4 Biography:
Manolis G.H. Katevenis was born in Athens, Greece, in 1955;
his parents were from Samos Island, in the Eastern Aegean Sea.
He received his undergraduate degree
in Mechanical and Electrical Engineering in 1978 from NTUA, Athens, Greece,
and his M.Sc. (1980) and Ph.D. (1983) degrees in Computer Science
from the University of California, Berkeleyi, USA. From
January 1984 to March 1985 he was Assistant Professor of Computer
Science at Stanford University, Stanford, California, USA.
Since September 1985, he is with the
University of Crete, Dept. of
Computer Science, where he is currently a Professor;
according to an Award by the Secretary General of the Region of Crete
in 2003, Katevenis is recognized as
one of the three Principal Organizers of this Department.
Since 1985, he is also with the
Institute of Computer Science
(ICS), FORTH,
Heraklion, Crete, where he is currently Deputy Director, and the
Head of the
Computer Architecture and VLSI Systems
(CARV) Laboratory.
In 2012, he was elected Member of
Academia Europaea -
The Academy of Europe.
Katevenis was, in 2003-2004, a founding partner of
HiPEAC,
the European Network of Excellence on
High-Performance and Embedded Architecture and Compilation,
and is a member of its Steering Committee since then.
In 2011, he was one of the three founders of EuReCCA,
the European Research Center on Computer Architecture,
which gave birth, in 2015,
to EuroLab-4-HPC.
Katevenis is considered among the leading European Computer Architects,
and recognized as the "father" of this field in his country, Greece.
His key contributions in RISC architectures,
interconnection networks, and interprocessor communication
have appeared in more than 90 publications,
and have received more than 3100 citations,
with an h-index of 30.
He has been principal investigator for over 30 RDI projects,
with a total budget of over 15 Million Euro.
Katevenis has been on the Technical Program Committees (PC's)
or in other leading roles for more than 40 international conferences,
he has given more than 60 conference talks and invited lectures,
he has taught 16 different courses (8 of them graduate),
having developed at least 5 of them,
and he has supervised 40 graduate theses,
with some of the currently most prominent Greek computer architects
(including two recipients of the ACM Maurice Wilkes award)
being alumni of his.
His interests are in:
Computer Architecture – Scalable, Low-Power,
Manycore / Multiprocessor / Warehouse-Scale System Architecture
for High Performance Computing (HPC) and Big Data,
Exascale Computing, RISC-V;
Interprocessor Communication, Memory and Protection Architecture;
Interconnection Network Architecture; and
VLSI Systems.
During his doctoral studies (1980-83)
under Carlo Sequin and David Patterson,
Katevenis designed the micro-architecture of the RISC-I and RISC-II chips,
and was the chief implementor of the RISC-II
single-chip microprocessor at U.C.Berkeley
(precursor of the SUN SPARC architecture),
and for this thesis he received the 1983
Sakrison Memorial Prize
and the 1984
ACM Doctoral Dissertation Award.
The RISC ideas were adopted by the entire microprocessor industry
and revolutionized this sector of technology in the late 80's.
In 2015, the RISC Project was recognized as an IEEE Milestone,
and in 2017 David Patterson, together with John Hennessy,
received the ACM Turing Award for having led the RISC developments.
After Berkeley,
Katevenis consulted for AMD during the design of the "AMD-29000"
RISC microprocessor, for Daisy Systems during the design of a
hardware accelerator, for two other companies during the design
of very-high speed RISC processors in ECL and GaAs, for a
Storage Area Networking (SAN) company, and for DEC, SRC,
where he did the preliminary switch design for "Autonet",
precursor of DEC's "ATM GigaSwitch". In 1987, during the
first meetings of the IEEE Standard 1596-1992 Scalable Coherent
Interface (SCI) Committee, he was the first to propose using
point-to-point connections rather than a bus architecture.
Katevenis made key world-wide contributions in the last 33 years
in interconnection networks,
which are central to implementing such diverse technologies as
internet routers, multicore chips,
datacenter clusters, and supercomputers.
Between 1985 and 1991, he made pioneering contributions in
per-flow queueing, backpressure, congestion tolerance,
and weighted round-robin scheduling,
yielding weighted max-min fairness in switches for high speed networks
–topics whose industrial application
is seen one or two decades later.
In 1991 and 1992, he worked on switch design for
multiprocessor interconnection networks.
Between 1996 and 1998, Katevenis was the technical leader of the design of
ATLAS I, a 6-million-transistor single-chip
16x16 ATM switch, implemented in 0.35-micron CMOS by ST Microelectronics,
featuring 10 Gb/s throughput, sub-microsecond cut-through latency,
and credit-based flow control (backpressure) at the granularity of
32 thousand virtual channels. In 1998-2001, he introduced
wormhole IP over ATM, and led the design of
pipelined heap management for schedulers in multi-gigabit
weighted fair queueing, and hardware for managing thousands
of queues in DRAM at 10 Gb/s line rate. In 2002-2005, his research
concerned the architecture of –and congestion management in–
non-blocking switching fabrics with internal backpressure,
and distributed scheduling in buffered crossbars. From 2006 to 2011,
he worked on networks-on-chip (NoC),
including the micro-architecture of high-radix on-chip crossbar switches.
In parallel computing, Katevenis was among the pioneers in developing
low-latency explicit interprocessor communication techniques.
Katevenis' work in this area started in 1993-95,
when he led the Telegraphos project in FORTH-ICS,
where workstation clustering prototypes were designed and built,
based on remote-write, remote-DMA, and remote-enqueue operations,
including processor-network interfaces
for protected user-level communication.
Since 2006, his research concerns
interprocessor communication, memoryi, and protection architecture
in chip multiprocessors and
in multi-chip, multi-blade, and multi-rack scalable systems.
In the SARC project,
he led the design of an architecture and FPGA prototype
that unifies explicit and implicit communication
by integrating the network interface with the cache controller,
basing their common operation on a
configurable event-response harware mechanism.
In the ENCORE project, his group built prototypes of
cache-optimized remote DMA and bare-metal runtime
for systems with hundreds of cores but no cache coherence.
Since 2013, in the
EuroServer, ExaNeSt, ExaNoDe, EcoScale, and EuroEXA
group of projects (where ExaNeSt is coordinated by Katevenis),
his group builds prototypes of scalable, compact, and low-power
processor and accelerator modules for
High Performance Computing (HPC) and Big Data sytems.
They are based on 64-bit ARM cores and
they use the UNIMEM architecture
of a global address space that spans multiple coherence islands
and that features
remote load/store, remote page borrowing,
zero-copy protected user-level remote DMA,
remote interrupts, mailboxes, and shared virtualized storage and I/O.
The prototype that the Lab is currently building
aims at one thousand processor cores in 250 FPGAs,
with a total of 4 TBytes of DRAM and 16 TBytes of SSD
distributed across it.
A full Linux software stack is running on it,
including our own MPI library optimized for user-level RDMA,
and the partners of the projects
run entire real HPC Applications on the system.
For more information, see:
http://users.ics.forth.gr/~kateveni
1.5 Selected Publications:
RISC Architectures:
J24
(JSA'14: the Formic 64-FPGA Prototype,
emulating a 520-core heterogeneous manycore)
2. Publications
last updated: December 2018
Citations:
Google Scholar Profile:
scholar.google.com/citations?user=E2-GshsAAAAJ
(on 14 December 2018, shows 3180 citations,
h-index = 30,
i10-index = 57).
2.1 Books, Edited Books, Translated Books:
- B4
-
M. Katevenis, M. Martonosi, C. Kozyrakis, O. Temam, T. Ungerer (Eds.):
Proceedings of the 6th International Conference on
High Performance and Embedded Architectures and Compilers -
HiPEAC 2011,
ACM Digital Library, ISBN: 978-1-4503-0241-8,
Heraklion, Crete, Greece, 24-26 January 2011, 223 pages.
- B3
-
P. Stenstrom, M. Dubois, M. Katevenis, R. Gupta, T. Ungerer (Eds.):
Proceedings, Third International Conference on
High Performance Embedded Architectures and Compilers -
HiPEAC 2008,
Goteborg, Sweden, Jan. 2008, 400 pages;
LNCS 4917, Springer, ISSN 0302-9743, ISBN 978-3-540-77559-1.
- B2
-
M. Mano:
"Digital Design",
Prentice-Hall, 1984, ISBN 0-13-212333-9.
Greek translation by M. Katevenis
with the assistance of a group of graduate students,
Technical Chamber of Greece Editions, 1986, 592 pages.
- B1
-
M. Katevenis:
"Reduced Instruction Set Computer Architectures for VLSI",
1984
ACM Doctoral Dissertation Award,
MIT Press, ISBN 0-262-11103-9, 1985.
2.2 Book Chapters (full-text reviewed):
- BC4
-
S. Kavadias, M. Katevenis, D. Pnevmatikatos:
"Network Interface Design for Explicit Communication
in Chip Multiprocessors",
Chapter 10 in the book:
Designing Network-on-Chip Architectures in the Nanoscale Era,
J. Flich and D. Bertozzi (Eds.),
CRC Press - Taylor & Francis Groupa, ISBN: 978-1-4398-3710-8, 2011,
pp. 325-351.
- BC3
-
M. Katevenis:
"RISC Architectures",
Chapter 20 in the book:
Parallel and Distributed Computing Handbook,
A. Zomaya Ed., McGraw-Hill, ISBN 0-07-073020-2, 1995, pp. 595-620.
- BC2
-
M. Katevenis:
"The Nature of General-Purpose Computations",
Chapter 2 (pp. 13-34) in the book:
Reduced Instruction Set Computers,
W. Stallings, Editor, IEEE Computer Society Press Tutorial,
2nd Edition, ISBN 0-8186-8943-9, 1990,
pp. 13-34.
- BC1
-
M. Katevenis, C. Sequin, D. Patterson, R. Sherburne:
"RISC: Effective Architectures for VLSI Computers",
Chapter 2 in the book:
VLSI Electronics: Microstructure Science - Vol. 14: VLSI Design,
N. Einspruch, Editor, Academic Press, ISBN 0-12-234114-7, 1986,
pp. 35-79.
2.3 Patents, Patent Applications:
- PA4
-
M. Katevenis:
"Dynamic Max-Min Fair Rate Regulation Apparatuses, Methods, and Systems",
USA Patent expected to issue on 18 Dec. 2018,
with projected patent number 10,158,574.
Foundation for Research and Technology -- Hellas (FORTH).
Priority date: 24 Sep. 2014.
The Application had been published:
patents.google.com/patent/US20160087899A1/en
- PA3
-
M. Katevenis, E. Markatos, P. Vatsolaki:
"Notification of Message Arrival in a Parallel Computer System",
Foundation for Research and Technology -- Hellas (FORTH),
Heraklion Crete Greece,
European Patent Application No. 97410036.4-2201,
19 March 1997,
Publication No. EP 0866406 A1 –
the Remote Enqueue operation.
- PA2
-
M. Katevenis:
"A High-Throughput Data Buffer",
Foundation for Research and Technology -- Hellas (FORTH),
Heraklion Crete Greece,
USA Patent Number 5,774,653,
2 August 1994,
issued 30 June 1998 –
Pipelined Memory Shared Buffer for Switching.
- PA1
-
M. Katevenis:
"Method for processor simulation",
ACRI S.A., Lyon, France,
European Patent Application EP19920420162,
18 May 1992,
Publication No. EP 0570646 A1 –
on-the-flight binary translation
from a foreign to the local instruction set.
2.4 Journal Publications - full-text reviewed:
- J27
-
M. Katevenis, et al.:
"Next generation of Exascale-class systems: ExaNeSt project
and the status of its interconnect and storage development",
Microprocessors and Microsystems: Embedded Hardware Design
(MICPRO), Elsevier,
vol. 61, Sep. 2018, pp. 58-71;
DOI: 10.1016/j.micpro.2018.05.009
- J26
-
N. Chrysos, L. Chen, C. Kachris, M. Katevenis:
"Discharging the Network from its Flow Control Headaches:
Packet Drops and HOL Blocking",
IEEE/ACM Transactions on Networking (ToN),
vol. 24, no. 1, February 2016, pp. 15-28;
DOI: 10.1109/TNET.2014.2378012
- J25
-
G. Passas, M. Katevenis, D. Pnevmatikatos:
"The Combined Input-Output Queued Crossbar Architecture
for High-Radix On-Chip Switches",
IEEE Micro,
vol. 35, no. 6, November-December 2015, pp. 38-47
(earlier published on-line: vol. PP, no. 99, June 2014);
DOI: 10.1109/MM.2014.56
- J24
-
S. Lyberis, G. Kalokerinos, M. Lygerakis, V. Papaefstathiou,
I. Mavroidis, M. Katevenis, D. Pnevmatikatos, D.S. Nikolopoulos:
"FPGA prototyping of emerging manycore architectures
for parallel programming research using Formic boards",
Journal of Systems Architecture (JSA), Elsevier,
vol. 60, issue 6, June 2014, pp. 481-493;
DOI: 10.1016/j.sysarc.2014.03.002
- J23
-
C. Kachris, G. Nikiforos, V. Papaefstathiou, S. Kavadias, M. Katevenis:
"NP-SARC:
Scalable network processing in the SARC multi-core FPGA platform",
Journal of Systems Architecture (JSA), Elsevier,
vol. 59, issue 1, January 2013, Pages 39-47;
DOI: 10.1016/j.sysarc.2012.11.001
- J22
-
Giorgos Passas, Manolis Katevenis, Dionisios Pnevmatikatos:
"Crossbar NoCs Are Scalable Beyond 100 Nodes",
IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems
(TCAD), ISSN: 0278-0070,
vol. 31, issue 4, April 2012, pp. 573-585;
DOI: 10.1109/TCAD.2011.2176730
- J21
-
Dario Suarez Gracia, G. Dimitrakopoulos, T. Monreal Arnal,
M. Katevenis, V. Vinals Yufera:
"LP-NUCA: Networks-in-Cache
for High-Performance Low-Power Embedded Processors",
IEEE Transactions on Very Large Scale Integrated Systems
(TVLSI),
vol. 20, no. 8, August 2012, pp. 1510-1523
(earlier published on-line: vol. PP, no. 99, July 2011);
DOI: 10.1109/TVLSI.2011.2158249
- J20
-
S. Kavadias, M. Katevenis, M. Zampetakis, D. Nikolopoulos:
"Cache-Integrated Network Interfaces:
Flexible On-Chip Communication and Synchronization for Large-Scale CMPs",
Int. Journal of Parallel Programming (IJPP),
Springer, vol. 40, issue 6, December 2012, pp. 583-604;
(earlier published on-line: June 2011);
DOI: 10.1007/s10766-011-0173-6
- J19
-
G. Kalokerinos, V. Papaefstathiou, G. Nikiforos, S. Kavadias,
M. Katevenis, D. Pnevmatikatos, X. Yang:
"Prototyping a Configurable Cache/Scratchpad Memory
with Virtualized User-Level RDMA Capability",
Transactions on HiPEAC
(ToH),
vol. 5, no. 3, 2010.
- J18
-
N. Chrysos, M. Katevenis:
"Distributed WFQ scheduling converging to weighted max-min fairness",
Computer Networks (Elsevier), ISSN 13891286,
vol. 55, issue 3, Oct. 2010 (on-line), Feb. 2011 (in print),
pp. 792-806.
- J17
-
M. Katevenis, V. Papaefstathiou, S. Kavadias,
D. Pnevmatikatos, F. Silla, D. Nikolopoulos:
"Explicit Communication and Synchronization in SARC",
IEEE Micro,
vol. 30, no. 5, pp. 30-41, Sep./Oct. 2010.
- J16
-
D. Simos, I. Papaefstathiou, M. Katevenis:
"Building an FoC Using Large, Buffered Crossbar Cores",
IEEE Design & Test,
vol. 25, no. 6, pp. 538-548, Nov. 2008;
DOI: 10.1109/MDT.2008.159
- J15
-
A. Ioannou, M. Katevenis:
"Pipelined Heap (Priority Queue) Management
for Advanced Scheduling in High Speed Networks",
IEEE/ACM Transactions on Networking
(ToN),
vol. 15, no. 2, pp. 450-461, April 2007;
DOI: 10.1109/TNET.2007.892882
- J14
-
G. Sapountzis, M. Katevenis:
"Benes Switching Fabrics with O(N)-Complexity Internal Backpressure",
IEEE Communications Magazine
vol. 43, no. 1, pp. 88-94, January 2005.
- J13
-
E. Markatos, D. Pnevmatikatos, M. Flouris, M. Katevenis:
"Web-Conscious Storage Management for Web Proxies",
IEEE/ACM Transactions on Networking
(ToN),
vol. 10, no. 6, pp. 735-748, Dec. 2002;
DOI: 10.1109/TNET.2002.804836
- J12
-
M. Katevenis, Iakovos Mavroidis, G. Sapountzis,
E. Kalyvianaki, Ioannis Mavroidis, G. Glykopoulos:
"Wormhole IP over (Connectionless) ATM",
IEEE/ACM Transactions on Networking
(ToN),
vol. 9, no. 5, pp. 650-661, October 2001;
DOI: 10.1109/90.958332
- J11
-
M. Katevenis, E. Markatos, P. Vatsolaki, C. Xanthaki:
"The Remote Enqueue Operation on Networks of Workstations",
Informatica -
an International Journal of Computing and Informatics,
ISSN 0350-5596, 23(1), pp. 29-39, April 1999.
- J10
-
G. Kornaros, D. Pnevmatikatos, P. Vatsolaki, G. Kalokerinos,
C. Xanthaki, D. Mavroidis, D. Serpanos, M. Katevenis:
"ATLAS I: Implementing a Single-Chip ATM Switch with Backpressure",
IEEE Micro,
vol. 19, no. 1, pp. 30-41, Jan/Feb. 1999.
- J9
-
D. Serpanos, M. Katevenis, E. Spyridakis:
"ATLAS I: Building Block for ATM Networks with Credit-based Flow Control",
IEICE Trans. on Communications,
Japan, 1998.
- J8
-
M. Katevenis, D. Serpanos, G. Dimitriadis:
"ATLAS I: A Single-Chip, Gigabit ATM Switch with
HIC/HS Links and Multi-Lane Back-Pressure",
Microprocessors and Microsystems, Elsevier,
vol. 21, no. 7-8, pp. 481-490,
March 1998;
DOI: 10.1016/S0141-9331(98)00041-6
- J7
-
M. Katevenis, E. Markatos, G. Kalokerinos, A. Dollas:
"Telegraphos:
A Substrate for High Performance Computing on Workstation Clusters",
Journal of Parallel and Distributed Computing
(JPDC),
Academic Press, vol. 43, no. 2, pp. 94-108, June 1997;
DOI: 10.1006/jpdc.1997.1334
- J6
-
M. Katevenis, P. Vatsolaki, V. Chalkiadakis:
"Credit-Flow-Controlled ATM over HIC Links
in the ASICCOM "ATLAS I" Single-Chip Switch",
Real-Time Magazine,
vol. 96, no. 3, pp. 65-72, July 1996.
- J5
-
M. Katevenis, S. Sidiropoulos, C. Courcoubetis:
"Weighted Round-Robin Cell Multiplexing
in a General-Purpose ATM Switch Chip",
IEEE Journal on Selected Areas in Communications
(JSAC),
Vol. 9, No. 8, pp. 1265-1279, October 1991;
DOI: 10.1109/49.105173
- J4
-
M. Katevenis:
"Fast Switching and Fair Control of Congested Flow
in Broad-Band Networks",
IEEE Journal on Selected Areas in Communications
(JSAC),
Vol. 5, No. 8, pp. 1315-1326, October 1987.
- J3
-
R. Sherburne, M. Katevenis, D. Patterson, C. Sequin:
"A 32-Bit NMOS Microprocessor with a Large Register File",
IEEE Journal of Solid State Circuits
(JSSC),
Vol. 19, No. 5, pp. 682-689, October 1984;
DOI: 10.1109/JSSC.1984.1052208
- J2
-
M. Katevenis, R. Sherburne, D. Patterson and C. Sequin:
"The RISC II Micro-Architecture",
Journal of VLSI and Computer Systems,
Computer Science Press Inc.,
vol. 1, issue 2, September 1984, pp. 138-152.
- J1
-
D. Fitzpatrick, J. Foderaro, M. Katevenis, H. Landman, D. Patterson,
J. Peek, Z. Peshkess, C. Sequin, R. Sherburne, K. VanDyke:
"A RISCy Approach to VLSI",
VLSI Design Magazine,
Vol. II, No. 4, 4th qu. 1981, pp. 14-20.
2.5 Conference and Major Workshop Proceedings Publications
- full-text reviewed:
- C58
-
D. Giannopoulos, N. Chrysos, E. Mageiropoulos, G. Vardas, L. Tzanakis,
and M. Katevenis:
"Accurate Congestion Control for RDMA Transfers",
Proc. of the
12th ACM/IEEE Int. Symposium on Networks-on-Chips
(NOCS 2018),
Turin, Italy, 4-5 Oct. 2018, pp. 1-8;
DOI: 10.1109/NOCS.2018.8512155
- C57
-
R. Ammendola, A. Biagioni, P. Cretaro, O. Frezza, F. Lo Cicero,
A. Lonardo, M. Martinelli, P.S. Paolucci, E. Pastorelli, F. Pisani,
F. Simula, P. Vicini, J. Navaridas,
F. Chaix, N. Chrysos, M. Katevenis, V. Papaefstathiou:
"Low Latency Network and Distributed Storage
for Next Generation HPC Systems: the ExaNeSt project",
Journal of Physics: Conference Series,
IOP Publishing, vol. 898, track 6, no. 082045, October 2017;
DOI: 10.1088/1742-6596/898/8/082045
- C56
-
E. Vasilakis, I. Sourdis, V. Papaefstathiou, A. Psathakis, M. Katevenis:
"Modeling Energy-Performance Tradeoffs in ARM big.LITTLE Architectures",
Proc. of the 27th Int. Symposium on
Power and Timing Modeling, Optimization and Simulation
(PATMOS'17), IEEE,
Thessaloniki, Greece, 25-27 Sep. 2017;
DOI: 10.1109/PATMOS.2017.8106950
- C55
-
R. Ammendola, A. Biagioni, P. Cretaro, O. Frezza, F. Lo Cicero,
A. Lonardo, M. Martinelli, P. S. Paolucci, E. Pastorelli, F. Simula,
P. Vicini, G. Taffoni, J, Goodacre, M. Lujan, J. Navaridas, J. P. Saiz,
N. Chrysos, and M. Katevenis:
"The next Generation of Exascale-class Systems: the ExaNeSt Project",
Proc. of the
Euromicro Conference on Digital System Design
(DSD'17), IEEE,
Vienna, Austria, 30 Aug. - 1 Sep. 2017;
DOI: 10.1109/DSD.2017.20
- C54
-
M. Katevenis, et al.:
"The ExaNeSt Project: Interconnects, Storage, and Packaging
for Exascale Systems",
Proc. of the
Euromicro Conference on Digital System Design
(DSD'16), IEEE,
Limassol, Cyprus, 31 Aug. - 2 Sep. 2016;
DOI: 10.1109/DSD.2016.106
- C53
-
A. Psathakis, V. Papaefstathiou, N. Chrysos, F. Chaix,
E. Vasilakis, D. Pnevmatikatos, M. Katevenis:
"A Systematic Evaluation of Emerging Mesh-like CMP NoCs",
Proc. of the
11th ACM/IEEE Symposium on Architectures
for Networking and Communications Systems
(ANCS'15),
Oakland, CA USA, 7-8 May 2015, pp. 159-170;
DOI: 10.1109/ANCS.2015.7110129
- C52
-
Y. Durand, P. Carpenter, S. Adami, A. Bilas,
D. Dutoit, A. Farcy, G. Gaydadjiev, J. Goodacre,
M. Katevenis, M. Marazakis, E. Matus, I. Mavroidis, J. Thomson:
"EUROSERVER: Energy Efficient Node for European Micro-servers",
Proc. of the
17th Euromicro Conference on Digital Systems Design
(DSD 2014),
Verona, Italy, 27-29 August 2014, pp. 206-213;
DOI: 10.1109/DSD.2014.15
- C51
-
A. Psathakis, V. Papaefstathiou, M. Katevenis, D. Pnevmatikatos:
"Design space exploration for fair resource-allocated NoC architectures",
Proc. of the
IEEE Int. Conf. on Embedded Computer Systems:
Architectures, Modeling and Simulation
(SAMOS XIV),
Samos, Greece, 14-17 July 2014, ISBN: 978-1-4799-3770-7, pp. 141-148;
DOI: 10.1109/SAMOS.2014.6893205
- C50
-
V. Papaefstathiou, M. Katevenis, D. S. Nikolopoulos, D. Pnevmatikatos:
"Prefetching and Cache Management using Task Lifetimes",
Proc. of the
27th ACM International Conference on Supercomputing
(ICS'13),
Eugene, Oregon, USA, 10-14 June 2013, pp. 325-334;
DOI: 10.1145/2464996.2465443
- C49
-
S. Lyberis, G. Kalokerinos, M. Lygerakis, V. Papaefstathiou, D. Tsaliagkos,
M. Katevenis, D. Pnevmatikatos, D. Nikolopoulos:
"Formic:
Cost-efficient and Scalable Prototyping of Manycore Architectures",
Proc. of the
20th IEEE Int. Symposium on
Field-Programmable Custom Computing Machines
(FCCM'12),
Toronto Canada, May 2012, pp. 61-64;
DOI: 10.1109/FCCM.2012.20
- C48
-
Yanping Gao, C. Kachris, M. Katevenis:
"An Efficient Sequential Iterative Matching Algorithm for CIOQ Switches",
Proc. of the
16th IEEE Symposium on Computers and Communications
(ISCC 2011),
Kerkyra (Corfu), Greece, 28 June - 1 July 2011, pp. 558-563.
- C47
-
G. Passas, M. Katevenis, D. Pnevmatikatos:
"VLSI Micro-Architectures for High-Radix Crossbar Schedulers",
Proc. of the
5th ACM/IEEE Int. Symposium on Networks-on-Chips
(NOCS 2011),
ISBN 978-1-4503-0720-8,
Pittsburgh, PA, USA, 1-4 May 2011, 8 pages.
- C46
-
P. Tendulkar, V. Papaefstathiou, G. Nikiforos, S. Kavadias,
D. Nikolopoulos, M. Katevenis:
"Fine-Grain OpenMP Runtime Support
with Explicit Communication Hardware Primitives",
Proc. of the
Design, Automation, and Test in Europe Conference
(DATE 2011),
ISBN: 978-3-9810801-7-9, Grenoble, France, 14-18 March 2011, 4 pages.
- C45
-
Xiaojun Yang, C. Kachris, M. Katevenis:
"Efficient Implementation for CIOQ Switches
with Sequential Iterative Matching Algorithms",
Proc. of the
IEEE Int. Conf. on Field-Programmable Technology,
(FPT 2010),
doi: 10.1109/FPT.2010.5681453, Beijing, China, December 2010, pp. 433-436.
- C44
-
C. Kachris, G. Nikiforos, S. Kavadias, V. Papaefstathiou, M. Katevenis:
"Network Processing in Multi-core FPGAs
with Integrated Cache-Network Interface",
Proc. of the
IEEE Int. Conf. on Reconfigurable Computing and FPGAs
(Reconfig 2010),
Cancun, Mexico, December 2010.
- C43
-
S. Kavadias, M. Katevenis, M. Zampetakis, D. Nikolopoulos:
"On-chip Communication and Synchronization Mechanisms
with Cache-Integrated Network Interfaces",
Proc. of the
7th ACM Int. Conf. on Computing Frontiers
(CF 2010),
Bertinoro, Italy, 17-19 May 2010, pp. 217-226,
doi.acm.org/10.1145/1787275.1787328
- C42
-
G. Passas, M. Katevenis, D. Pnevmatikatos:
"A 128x128x24Gb/s Crossbar, Interconnecting 128 Tiles in a Single Hop,
and Occupying 6% of their Area",
Proc. of the
4th ACM/IEEE Int. Symposium on Networks-on-Chips
(NOCS 2010),
Grenoble, France, 3-6 May 2010, pp. 87-95,
doi: 10.1109/NOCS.2010.37;
IEEE Computer Society ISBN 978-0-7695-4049-8.
- C41
-
G. Kalokerinos, V. Papaefstathiou, G. Nikiforos, S. Kavadias,
M. Katevenis, D. Pnevmatikatos, Xiaojun Yang:
"FPGA Implementation of a Configurable Cache/Scratchpad Memory
with Virtualized User-Level RDMA Capability",
Proc. of the
IEEE Int. Conf. on Embedded Computer Systems:
Architectures, Modeling and Simulation
(IC-SAMOS 2009),
Samos, Greece, 20-23 July 2009, ISBN 978-1-4244-4501-1, pp. 149-156.
- C40
-
V. Papaefstathiou, D. Pnevmatikatos, M. Marazakis, G. Kalokairinos,
A. Ioannou, M. Papamichael, S. Kavadias, G. Mihelogiannakis, M. Katevenis:
"Prototyping Efficient Interprocessor Communication Mechanisms",
Proc. of the
IEEE Int. Conf. on Embedded Computer Systems:
Architectures, Modeling and Simulation
(IC-SAMOS 2007),
Samos, Greece, 16-19 July 2007, pp. 26-33.
- C39
-
N. Chrysos, M. Katevenis:
"Crossbars with Minimally-Sized Crosspoint Buffers",
Proc. of the
IEEE Int. Conf. on High Performance Switching and Routing,
(HPSR 2007),
Brooklyn, NY, USA, 30 May - 1 June 2007.
- C38
-
G. Passas, M. Katevenis:
"Asynchronous Operation of Bufferless Crossbars",
Proc. of the
IEEE Int. Conf. on High Performance Switching and Routing,
(HPSR 2007),
Brooklyn, NY, USA, 30 May - 1 June 2007,
ISBN 1-4244-1206-4, paper ID 1569017531.pdf.
- C37
-
G. Michelogiannakis, D. Pnevmatikatos, M. Katevenis:
"Approaching Ideal NoC Latency with Pre-Configured Routes",
Proc. of the
1st ACM/IEEE Int. Symposium on Networks-on-Chips
(NOCS 2007),
Princeton, NJ, USA, 7-9 May 2007, pp. 153-162.
- C36
-
M. Katevenis, G. Passas:
"Packet Mode Scheduling in Buffered Crossbar (CICQ) Switches",
Proc. of the IEEE Workshop - later called
IEEE Int. Conf. on High Performance Switching and Routing,
(HPSR 2006),
Poznan, Poland, 7-9 June 2006, pp. 105-112, ISBN 0-7803-9570-0.
- C35
-
N. Chrysos, M. Katevenis:
"Preventing Buffer-Credit Accumulations
in Switches with Shared Small Output Queues",
Proc. of the IEEE Workshop - later called
IEEE Int. Conf. on High Performance Switching and Routing,
(HPSR 2006),
Poznan, Poland, 7-9 June 2006, pp. 409-416, ISBN 0-7803-9570-0.
- C34
-
N. Chrysos, M. Katevenis:
"Scheduling in Non-Blocking Buffered Three-Stage Switching Fabrics",
Proc. of the IEEE Infocom 2006 Conference,
Barcelona, Spain, 23-29 Apr. 2006, 13 pages, CDROM paper ID 13_01.
- C33
-
N. Chrysos, M. Katevenis:
"Scheduling in Switches with Small Internal Buffers",
Proc. of the IEEE Globecom 2005 Conference,
St. Louis, MO, USA, 28 Nov. - 2 Dec. 2005, 6 pages, CDROM paper ID gc21_3.
- C32
-
M. Katevenis, G. Passas:
"Variable-Size Multipacket Segments
in Buffered Crossbar (CICQ) Architectures",
Proc. of the IEEE Int. Conf. on Communications
(ICC 2005),
Seoul, Korea, 16-20 May 2005, CR-ROM paper ID "09GC08-4", 6 pages.
- C31
-
N. Chrysos, M. Katevenis:
"Multiple Priorities in a Two-Lane Buffered Crossbar",
Proc. of the IEEE Globecom 2004 Conference,
Dallas, TX, USA, 29 Nov. - 4 Dec. 2004, CR-ROM paper ID "GE15-3", 7 pages.
- C30
-
M. Katevenis, G. Passas, D. Simos, I. Papaefstathiou, N. Chrysos:
"Variable Packet Size Buffered Crossbar (CICQ) Switches",
Proc. of the IEEE Int. Conf. on Communications
(ICC 2004),
Paris, France, June 2004, vol. 2, pp. 1090-1096.
- C29
-
N. Chrysos, M. Katevenis:
"Weighted Fairness in Buffered Crossbar Scheduling",
Proc. of the IEEE Workshop - later called
IEEE Int. Conf. on High Performance Switching and Routing,
(HPSR 2003),
Torino, Italy, June 2003, pp. 17-22;
- C28
-
G. Sapountzis, M. Katevenis:
"Benes Switching Fabrics with O(N)-Complexity Internal Backpressure",
Proc. of the IEEE Workshop - later called
IEEE Int. Conf. on High Performance Switching and Routing,
(HPSR 2003),
Torino, Italy, June 2003, pp. 11-16.
- C27
-
A. Ioannou, M. Katevenis:
"Pipelined Heap (Priority Queue) Management
for Advanced Scheduling in High Speed Networks",
Proc. of the IEEE Int. Conf. on Communications
(ICC 2001),
Helsinki, Finland, June 2001, pp. 2043-2047.
- C26
-
A. Nikologiannis, M. Katevenis:
"Efficient Per-Flow Queueing in DRAM at OC-192 Line Rate
using Out-of-Order Execution Techniques",
Proc. of the IEEE Int. Conf. on Communications
(ICC 2001),
Helsinki, Finland, June 2001, pp. 2048-2052.
- C25
-
E. Markatos, M. Katevenis, D. Pnevmatikatos, M. Flouris:
"Secondary Storage Management for Web Proxies",
Proc. 2nd USENIX Symposium on
Internet Technologies and Systems
(USITS 1999),
Boulder, CO USA, Oct. 1999, pp. 93-104.
- C24
-
G. Kornaros, D. Pnevmatikatos, P. Vatsolaki, G. Kalokerinos,
C. Xanthaki, D. Mavroidis, D. Serpanos, M. Katevenis:
"Implementation of ATLAS I: a Single-Chip ATM Switch with Backpressure",
Proc. of the IEEE Hot Interconnects 6 Symposium
(HotI 1998),
Stanford, California, USA, 13-15 August 1998, pp. 85-96.
- C23
-
M. Katevenis, D. Serpanos, E. Spyridakis:
"Credit-Flow-Controlled ATM for MP Interconnection:
the ATLAS I Single-Chip ATM Switch",
Proc. of the
4th IEEE Int. Symp. on High-Performance Computer Architecture
(HPCA 1998),
Las Vegas, NV USA, Feb. 1998,
IEEE Computer Soc. Press, ISBN 0-8186-8323-6, pp. 47-56.
- C22
-
E. Markatos, M. Katevenis, P. Vatsolaki:
"The Remote Enqueue Operation on Networks of Workstations",
Proceedings of the
Workshop on Communication and Architectural Support
for Network-Based Parallel Computing
(CANPC 1998),
Las Vegas, NV USA, 31 Jan. 1998,
Lecture Notes in Computer Science 1362, Springer-Verlag, pp. 1-14.
- C21
-
M. Katevenis, D. Serpanos, E. Spyridakis:
"Switching Fabrics with Internal Backpressure
using the ATLAS I Single-Chip ATM Switch",
Proc. of the IEEE GLOBECOM 1997 Conference,
Phoenix, AZ USA, Nov. 1997, pp. 242-246.
- C20
-
M. Katevenis, D. Serpanos, E. Markatos:
"Multi-Queue Management and Scheduling
for Improved QoS in Communication Networks",
Proc. of the European Multimedia Microprocessor Systems
and Electronic Commerce Conference
(EMMSEC 1997),
Florence, Italy, Nov. 1997, pp. 906-913.
- C19
-
G. Kornaros, C. Kozyrakis, P. Vatsolaki, M. Katevenis:
"Pipelined Multi-Queue Management in a
VLSI ATM Switch Chip with Credit-Based Flow Control",
Proc. of the 17th Conf. on Advanced Research in VLSI
(ARVLSI 1997),
Univ. of Michigan at Ann Arbor, MI USA, Sept. 1997,
IEEE Computer Soc. Press, ISBN 0-8186-7913-1, pp. 127-144.
- C18
-
M. Katevenis:
"Buffer Requirements of Credit-Based Flow Control
when a Minimum Draining Rate is Guaranteed",
Proc. of the 4th IEEE Workshop on
Architecture and Implementation of High Perf. Commun. Subsystems
(HPCS 1997),
Chalkidiki, Greece, June 1997.
- C17
-
D. Serpanos, M. Katevenis, E. Spyridakis:
"ATLAS I: Building Block for ATM Networks
with Credit-Based Flow Control",
Proc. of the 4th IEEE Workshop on
Architecture and Implementation of High Perf. Commun. Subsystems
(HPCS 1997),
Chalkidiki, Greece, June 1997.
- C16
-
E. Markatos, M. Katevenis:
"User-Level DMA without Operating System Kernel Modification",
Proc. of the
3rd IEEE Int. Symp. on High-Performance Computer Architecture
(HPCA 1997),
San Antonio, TX USA, Feb. 1997, pp. 322-331.
- C15
-
M. Katevenis, P. Vatsolaki, D. Serpanos, E. Markatos:
"ATLAS I: A Single-Chip ATM Switch for NOWs",
Proc. of the
Workshop on Communication and Architectural Support
for Network-Based Parallel Computing
(CANPC 1997),
San Antonio, TX USA, Feb. 1997,
Lecture Notes in Computer Science 1199, Springer-Verlag, pp.88-101.
- C14
-
M. Katevenis, P. Vatsolaki:
"ATLAS I: A Single-Chip ATM Switch with
HIC Links and Multi-Lane Back-Pressure",
Proc. of the
6th Annual OMI Conference: Embedded Microprocessor Systems,
(EMSYS 1996),
Berlin, Germany, Sep. 1996,
IOS Press, ISBN 90-5199-300-5, pp. 126-136.
- C13
-
M. Katevenis, D. Serpanos, P. Vatsolaki:
"ATLAS I: A General-Purpose, Single-Chip ATM Switch
with Credit-Based Flow Control",
Proc. of the IEEE Hot Interconnects IV Symposium
(HotI 1996),
Stanford Univ., CA, USA, Aug. 1996, pp. 63-73.
- C12
-
E. Markatos, M. Katevenis:
"Telegraphos: High-Performance Networking
for Parallel Processing on Workstation Clusters",
Proc. of the
2nd IEEE Int. Symp. on High-Performance Computer Architecture
(HPCA 1996),
San Jose, CA USA, February 1996, pp.144-153.
- C11
-
M. Katevenis, P. Vatsolaki, A. Efthymiou:
"Pipelined Memory Shared Buffer for VLSI Switches",
Proc. of the ACM SIGCOMM '95 Conference
(SIGCOMM 1995),
Cambridge, MA USA, 30 August - 1 Sep. 1995, pp. 39-48.
- C10
-
M. Katevenis, P. Vatsolaki, A. Efthymiou, M. Stratakis:
"VC-level Flow Control and Shared Buffering
in the Telegraphos Switch",
Proc. of the IEEE Hot Interconnects III Symposium
(HotI 1995),
Stanford Univ., CA, USA, Aug. 1995.
- C9
-
M. Katevenis, N. Tzartzanis:
"Reducing the Branch Penalty
by Rearranging Instructions in a Double-Width Memory",
Proceedings of the
4th Int. Conf. on Architectural Support
for Progr. Languages and Oper. Systems
(ASPLOS 1991),
Santa Clara, California, April 1991, pp. 15-27.
- C8
-
A. Vladimirescu, D. Weiss, M. Katevenis, Z. Bronstein, A. Kfir,
K. Danuwidjaja, K. Ng, N. Jain, S. Lass:
"A Vector Hardware Accelerator with Circuit Simulation Emphasis",
Proceedings,
24th ACM/IEEE Design Automation Conference
(DAC 1987),
June 1987, pp. 89-94.
- C7
-
M. Katevenis, M. Blatt:
"Switch Design for Soft-Configurable WSI Systems",
Proc. of the
Conference on Advanced Research in VLSI
(ARVLSI 1985),
Univ. of North Carolina, Chapel Hill, May 1985.
- C6
-
R. Sherburne, M. Katevenis, D. Patterson, C. Sequin:
"A 32-Bit NMOS Microprocessor with a Large Register File",
Proceedings,
31st IEEE Int. Solid-State Circuits Conference
(ISSCC 1984),
San Francisco, February 1984, THAM 12.1, pp. 168-169.
- C5
-
R. Sherburne, M. Katevenis, D. Patterson, C. Sequin:
"Local Memory in RISCs",
Proceedings,
IEEE Int. Conf. on Computer Design: VLSI in Computers
(ICCD 1983),
New York, Nov. 1983, pp. 149-152.
- C4
-
M. Katevenis, R. Sherburne, D. Patterson and C. Sequin:
"The RISC II Micro-Architecture",
Proceedings of the IFIP TC10/WG10.5
Int. Conference on Very Large Scale Integration
(VLSI 1983),
Trondheim, Norway, 16-19 Aug. 1983,
North Holland Pub. Co., pp.349-359.
- C3
-
R. Sherburne, M. Katevenis, D. Patterson, C. Sequin:
"Datapath Design for RISC",
Proceedings,
Conference on Advanced Research in VLSI (ARVLSI),
(ARVLSI 1982),
M.I.T., Jan. 1982, pp. 53-62.
- C2
-
D. Fitzpatrick, J. Foderaro, M. Katevenis, H. Landman, D. Patterson,
J. Peek, Z. Peshkess, C. Sequin, R. Sherburne, K. VanDyke:
"VLSI Implementations of a Reduced Instruction Set Computer",
Proceedings of the VLSI Systems and Computations Conference --later called
Conference on Advanced Research in VLSI
(ARVLSI 1981),
Carnegie-Mellon Univ., October 1981,
Computer Science Press, pp. 327-336.
Also published in:
Computer Architecture News (ACM SIGARCH),
Vol. 10, No. 1, March 1982, pp. 28-32.
- C1
-
M. Katevenis, A. Arvillias, C. Halkias:
"Implementation of the FFT algorithm using the M6800 microprocessor",
Proc. of the IEEE Int. Symposium on Circuits and Systems,
(ISCAS 1979),
Tokyo Japan, July 1979, p. 973.
An extended version appeared in
Technika Chronika (ME-EE-NE section),
Technical Chamber of Greece, Athens, Apr. 1979, pp.9-16.
2.6 Other Workshop and Technical Report Publications:
[ExascaleHPC 2018]
M. Ploumidis, A. Psistakis, M. Asiminakis, P. Xirouchakis, M. Gianioudis,
P. Peristerakis, F. Chaix, V. Papaefstathiou, N. Chrysos, M. Katevenis:
"Exploiting the ExaNeSt Communication Primitives
for a High Performance MPI Library",
Presentation at the Workshop ExascaleHPC:
the ExaNoDe, ExaNeSt, EcoScale, and EuroEXA projects,
held in conjunction with the HiPEAC 2018 Conference,
Manchester, UK, 23 Jan. 2018;
www.exanest.eu/pub/ploumidis_exaWrksh18manch_exanestMPI.pdf
[AISTECS 2016]
M. Katevenis and N. Chrysos:
"Challenges and Opportunities in Exascale-Computing Interconnects",
Keynote Presentation at the
1st Int. Workshop on Advanced Interconnect Solutions and
Technologies for Emerging Computing Systems (AISTECS 2016),
held in conjunction with the HiPEAC 2016 Conference,
Prague, Czech Republic, 18 Jan. 2016;
mpsoc.unife.it/~aistecs/
[NOCS 2014]
A. Psathakis, V. Papaefstathiou, M. Katevenis, D. Pnevmatikatos:
"Design Trade-offs in Energy Efficient NoC Architectures",
Proc. 8th IEEE/ACM Int. Symp. on Networks on Chip (NOCS 2014),
Ferrara, Italy, 17-19 September 2014, pp. 186-187 (poster presentation).
[ANCS 2010]
N. Chrysos, L. Chen, C. Minkenberg, C. Kachris, M. Katevenis:
"End-to-end congestion management
for non-blocking multi-stage switching fabrics",
Proc. 2010 ACM/IEEE Symp. on
Architecture for Networking and Communications Systems (ANCS 2010),
San Diego, CA USA, 25-26 October 2010, pp. 6-7 (poster presentation);
DOI: 10.1145/1872007.1872016
[CLUSTER 2010]
C. Kachris, G. Nikiforos, V. Papaefstathiou, S. Kavadias, M. Katevenis:
"Low-latency Explicit Communication and Synchronization
in Scalable Multi-core Clusters",
Short paper and poster presented at the
IEEE Int. Conf. on Cluster Computing (CLUSTER 2010),
Hersonissos, Crete, Greece, 20-24 September 2010.
[HiPEAC 2010]
M. Duranton, S. Yehia, B. De Sutter, K. De Bosschere, A. Cohen,
B. Falsafi, G. Gaydadjiev, M. Katevenis, J. Maebe, H. Munk,
N. Navarro, A. Ramirez, O. Temam, M. Valero:
"The HiPEAC Vision",
Network of Excellence on
High Performance and Embedded Architecture and Compilation,
Spring 2010, 56 pages;
http://www.hipeac.net/roadmap
[full PDF at:
http://www.hipeac.net/system/files/hipeacvision.pdf ]
[SAMOS 2008]
M. Katevenis:
"Towards Unified Mechanisms for Inter-Processor Communication",
Keynote Presentation at the
IEEE Int. Conf. on Embedded Computer Systems:
Architectures, Modeling and Simulation (IC-SAMOS VIII),
Samos, Greece, 21-24 July 2008.
[Stamatis 2007]
M. Katevenis:
"Interprocessor Communication
seen as Load-Store Instruction Generalization",
Invited Paper in the Proc. of the
Stamatis Vassiliadis Symposium - The Future of Computing,
K. Bertels e.a. Editors,
Delft, The Netherlands, 28 Sep. 2007, pp. 55-68.
[ERCIM 2004]
M. Katevenis, N. Chrysos:
"New Crossbar directly switches Variable-Size Packets",
ERCIM News,
no. 57,
April 2004, pp. 58-59.
[EPY 1999]
G. Kornaros, D. Pnevmatikatos, D. Mavroidis, P. Vatsolaki, G. Kalokerinos,
C. Xanthaki, G. Dimitriadis, D. Serpanos, M. Katevenis:
"On Optimizing ATLAS I, a 10 Gbps ATM Switch",
Proc. 7th Panhellenic Informatics Conference,
Ioannina, Greece, August 1999.
Also in Advances in Informatics, Fotiadis/Nikolopoulos Eds,
World Scientific Publishing Co, ISBN 981-02-4192-5, pp. 164-177.
[ERCIM 1999]
M. Katevenis:
"Wormhole IP over ATM",
ERCIM News,
no. 37,
April 1999, p. 15.
[EPY 1995]
P. Vatsolaki, G. Kalokerinos, M. Stratakis, Ch. Xanthaki,
M. Ligerakis, G. Kornaros, A. Dollas, G. Papadourakis, M. Katevenis:
"The Implementation of Telegraphos:
a High Speed Communication Architecture" (In Greek),
Proceedings of the 5th Panhellenic Informatics Conference,
Athens Greece, December 1995.
[SCI 1995]
E. Markatos, M. Katevenis, G. Kalokerinos, D. Serpanos:
"An Efficient Processor-Network Interface
for Local Area Multiprocessors",
Proceedings of the 4th Int. Workshop on
SCI-based High-Performance Low-Cost Computing,
SCIzzL, Crete Greece, 3 October 1995, pp. 23-32.
[ERCIM 1995]
M. Katevenis, C. Georgis:
"The Labyrinth System",
ERCIM News,
no. 20,
Jan. 1995.
[Seq. Consist. 1993]
J. Goodman, M. Katevenis:
"A High-Speed Multiprocessor Network
for Delivering Requests to Memory in Processor Time-Stamp Order"
(method for achieving sequential consistency),
ESPRIT P6253 "SHIPS" Confidential Document,
summer 1993.
[Mem. Barrier 1992]
P. Vatsolaki, M. Katevenis:
"Implementation of the Memory Barrier
in Multi-Stage Processor-Memory Networks",
ESPRIT P6253 "SHIPS" Confidential Working Document,
version 1.0, FORTH-ICS, Heraklion, Crete, 29 Dec. 1992.
(Innovative design for the method to implement
the memory barrier operation
in the processor to memory interconnection network
of a parallel supercomputer).
[Switch 1992]
M. Katevenis, G. Kalokerinos, P. Vatsolaki, E. Neonakis, M. Stratakis:
"Internal Organizations of One-Cycle-Latency Crossbar Switch Chips",
ESPRIT P6253 "SHIPS" Confidential Working Document,
version 1.3, FORTH-ICS, Heraklion, Crete, 31 Dec. 1992.
(Design and evaluation
--at the gate netlist level, verified by simulation in Verilog--
of three different organizations for the switch chip
--in ECL gate-array technology, with 4 ns cycle time--
for processor to memory interconnection
in a parallel supercomputer).
[DEC Autonet 1988]
M. Katevenis:
"The Autonet Switch: Architecture & Register-Transfer-Level Design",
Internal Memo, DEC Systems Research Center,
Palo Alto, CA, USA, 40 pages, Jan. 1988.
(This was the preliminary switch design for "Autonet" --
a high-speed, self-configuring LAN using point-to-point links,
precursor of DEC's "ATM GigaSwitch").
[IEEE SCI 1987]
M. Katevenis:
"Draft Ideas for a Backplane Superbus",
Memo to the IEEE "Superbus" (later "SCI") Committee,
California, USA, 17 pages, 10 December 1987.
(The IEEE "Superbus" Study Group was formed in 1987
in order to standardize a backplane bus
in the 1 GByte/s throughput range.
This was the first proposal to the group
to base the new standard on a ring of point-to-point connections
rather than a bus.
The Study Group later adopted this idea,
renamed the project "Scalable Coherent Interface" (SCI),
and developed ANSI/IEEE Standard 1596 (1992),
which is based on rings of point-to-point connections).
[WSI 1986]
M. Katevenis, M. Blatt:
"Switch Design for Soft-Configurable WSI Systems",
Proceedings of the IFIP WG 10.5
Workshop on Wafer Scale Integration,
Grenoble, France, March 1986;
Saucier, Trilhe, Eds, North Holland Co, ISBN 0-444-70103-6, pp. 255-270.
[RISC 1980]
M. Katevenis:
"A Proposal for the LSI Implementation of the RISC I CPU
(using a 3-phase clock)",
U.C.Berkeley, CS Div., Internal Working Paper,
September 1980.
(This internal working paper has served as
the specification (block structure and timing)
for the VLSI design of the RISC I NMOS single-chip 32-bit processor).
3. Research Grants, Commercialization Efforts
last updated: December 2018
3.1 R&D Grants by the European Commission:
Research, Development, and Innovation projects
at FORTH-ICS,
funded by the European Commission
following an evaluation of competing proposals,
where Manolis Katevenis was/is
the Principal Investigator (PI) at FORTH-ICS,
or co-PI where noted as such: