Manolis Katevenis' Publications

March 2011

The publications of Manolis Katevenis are listed here, sorted by topic and in reverse chronological order. The topics and chronological periods are:

Inter-Processor Communication (IPC) and other recent publications (2007 - onwards; see also "Networks of workstations, parallel and distributed systems", 1992-99, below)
Packet Switch & Switching Fabric Architecture (mostly 2000 - 2008, plus part of the work of 1987-97)
ATLAS I: a 10 Gbps Single-Chip ATM Switch with Backpressure (1996 - 1999)
High-Speed Switching (1985 - 1995)
Networks of Workstations, Parallel and Distributed Systems (1992 - 1999)
Reduced Instruction Set Computer (RISC) Architectures (1980 - 1985, plus some work of 1990-95)
Other Topics (1979 - 2002)

Inter-Processor Communication (IPC) and other recent publications (2007 - ):

[GaoKK11] Yanping Gao, C. Kachris, M. Katevenis: "An Efficient Sequential Iterative Matching Algorithm for CIOQ Switches", Proc. of the 16th IEEE Symposium on Computers and Communications (ISCC 2011), Kerkyra (Corfu), Greece, 28 June - 1 July 2011, 6 pages.

[PaKP11nocs] G. Passas, M. Katevenis, D. Pnevmatikatos: "VLSI Micro-Architectures for High-Radix Crossbar Schedulers", Proc. 5th ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS 2011), ISBN 978-1-4503-0720-8, Pittsburgh, PA, USA, 1-4 May 2011, 8 pages.

[Tendu11] P. Tendulkar, V. Papaefstathiou, G. Nikiforos, S. Kavadias, D. Nikolopoulos, M. Katevenis: "Fine-Grain OpenMP Runtime Support with Explicit Communication Hardware Primitives", Proc. Design, Automation & Test in Europe (DATE 2011) Conf., ISBN: 978-3-9810801-7-9, Grenoble, France, 14-18 March 2011.

[KavKP11] S. Kavadias, M. Katevenis, D. Pnevmatikatos: "Network Interface Design for Explicit Communication in Chip Multiprocessors", chapter 10 (pp. 325-351) in the book: Designing Network-on-Chip Architectures in the Nanoscale Era, J. Flich and D. Bertozzi (Eds.), CRC Press - Taylor & Francis Groupa, ISBN: 978-1-4398-3710-8, 2011.

[HiPEAC11] M. Katevenis, M. Martonosi, C. Kozyrakis, O. Temam, T. Ungerer (Eds.): Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC'11), ACM Digital Library, ISBN: 978-1-4503-0241-8, Heraklion, Crete, Greece, 24-26 January 2011, 223 pages.

[YangKK10] Xiaojun Yang, C. Kachris, M. Katevenis: "Efficient Implementation for CIOQ Switches with Sequential Iterative Matching Algorithms", Proc. of the IEEE Int. Conf. on Field-Programmable Technology (FPT 2010), doi: 10.1109/FPT.2010.5681453, Beijing, China, December 2010, pp. 433-436.

[Kachris10reconfig] C. Kachris, G. Nikiforos, S. Kavadias, V. Papaefstathiou, M. Katevenis: "Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface", Proc. IEEE Int. Conf. on Reconfigurable Computing and FPGAs (Reconfig 2010), Cancun, Mexico, December 2010.

[ChryKa10cn] N. Chrysos, M. Katevenis: "Distributed WFQ scheduling converging to weighted max-min fairness", Computer Networks (Elsevier), ISSN 13891286, vol. 55, issue 3, Oct. 2010 (on-line), Feb. 2011 (in print), pp. 792-806.

[Chrysos10] N. Chrysos, L. Chen, C. Minkenberg, C. Kachris, M. Katevenis: "End-to-end congestion management for non-blocking multi-stage switching fabrics", Proc. 2010 ACM/IEEE Symp. on Architecture for Networking and Communications Systems (ANCS 2010), San Diego, CA USA, 25-26 October 2010, pp. 6-7 (poster presentation).

[Kate10micro] M. Katevenis, V. Papaefstathiou, S. Kavadias, D. Pnevmatikatos, F. Silla, D. Nikolopoulos: "Explicit Communication and Synchronization in SARC", IEEE Micro, vol. 30, no. 5, pp. 30-41, Sep./Oct. 2010, http://doi.ieeecomputersociety.org/10.1109/MM.2010.77, http://archvlsi.ics.forth.gr/ipc/

[Kachris10cluster] C. Kachris, G. Nikiforos, V. Papaefstathiou, S. Kavadias, M. Katevenis: "Low-latency Explicit Communication and Synchronization in Scalable Multi-core Clusters", Short paper and poster presented at the IEEE Int. Conf. on Cluster Computing (CLUSTER 2010), Hersonissos, Crete, Greece, 20-24 September 2010; http://archvlsi.ics.forth.gr/ipc/

[KKZN10] S. Kavadias, M. Katevenis, M. Zampetakis, D. Nikolopoulos: "On-chip Communication and Synchronization Mechanisms with Cache-Integrated Network Interfaces", Proc. 7th ACM Int. Conf. on Computing Frontiers (CF'10), Bertinoro, Italy, 17-19 May 2010, pp. 217-226, http://doi.acm.org/10.1145/1787275.1787328 (ranked, by the PC Co-Chairs, as one of the top three papers of the Conference).

[PaKP10] G. Passas, M. Katevenis, D. Pnevmatikatos: "A 128x128x24Gb/s Crossbar, Interconnecting 128 Tiles in a Single Hop, and Occupying 6% of their Area", Proceedings of the 4th ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS 2010), Grenoble, France, 3-6 May 2010, pp. 87-95; IEEE Computer Society ISBN 978-0-7695-4049-8.

[Kalok09] G. Kalokerinos, V. Papaefstathiou, G. Nikiforos, S. Kavadias, M. Katevenis, D. Pnevmatikatos, Xiaojun Yang: "FPGA Implementation of a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability", Proc. IEEE Int. Conf. on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2009), Samos, Greece, 20-23 July 2009, ISBN 978-1-4244-4501-1, pp. 149-156;

[Kate08] M. Katevenis: "Towards Unified Mechanisms for Inter-Processor Communication", Keynote Presentation at the IEEE Int. Conf. on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS VIII), Samos, Greece, 21-24 July 2008; http://archvlsi.ics.forth.gr/ipc/ipcUnif_katevenis_samos08.pdf

[HiPEAC08] P. Stenstrom, M. Dubois, M. Katevenis, R. Gupta, T. Ungerer (Eds.): Proceedings, Third International Conference on High Performance Embedded Architectures and Compilers - HiPEAC 2008, Goteborg, Sweden, Jan. 2008, 400 pages; LNCS 4917, Springer, ISSN 0302-9743, ISBN 978-3-540-77559-1.

[Kate07] M. Katevenis: "Interprocessor Communication seen as Load-Store Instruction Generalization", in The Future of Computing, essays in memory of Stamatis Vassiliadis, K. Bertels e.a. Editors, Delft, The Netherlands, 28 Sep. 2007, pp. 55-68; http://archvlsi.ics.forth.gr/ipc/

[Ppef07] V. Papaefstathiou, D. Pnevmatikatos, M. Marazakis, G. Kalokairinos, A. Ioannou, M. Papamichael, S. Kavadias, G. Mihelogiannakis, M. Katevenis: "Prototyping Efficient Interprocessor Communication Mechanisms", Proc. IEEE Int. Conf. on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS VII), Samos, Greece, 16-19 July 2007, pp. 26-33; http://archvlsi.ics.forth.gr/ipc/

Packet Switch & Switching Fabric Architecture:

[Simos08] D. Simos, I. Papaefstathiou, M. Katevenis: "Building an FoC Using Large, Buffered Crossbar Cores", IEEE Design & Test, vol. 25, no. 6, Nov. 2008.

[ChKa07] N. Chrysos, M. Katevenis: "Crossbars with Minimally-Sized Crosspoint Buffers", Proc. IEEE Int. Conf. on High Performance Switching and Routing (HPSR 2007), Brooklyn, NY, USA, 30 May - 1 June 2007; http://archvlsi.ics.forth.gr/bufxbar/

[PaKa07] G. Passas, M. Katevenis: "Asynchronous Operation of Bufferless Crossbars", Proc. IEEE Int. Conf. on High Performance Switching and Routing (HPSR 2007), Brooklyn, NY, USA, 30 May - 1 June 2007, ISBN 1-4244-1206-4, paper ID 1569017531.pdf; http://archvlsi.ics.forth.gr/bufxbar/

[MiPK07] G. Michelogiannakis, D. Pnevmatikatos, M. Katevenis: "Approaching Ideal NoC Latency with Pre-Configured Routes", Proc. 1st ACM/IEEE Int. Symposium on Networks-on-Chips (NOCS'07), Princeton, NJ, USA, 7-9 May 2007, pp. 153-162; http://archvlsi.ics.forth.gr/noc/

[IoKa07] A. Ioannou, M. Katevenis: "Pipelined Heap (Priority Queue) Management for Advanced Scheduling in High Speed Networks", IEEE/ACM Transactions on Networking (ToN), vol. 15, no. 2, April 2007, pp. 450-461; http://archvlsi.ics.forth.gr/muqpro/heapMgt.html

[PaKa06] M. Katevenis, G. Passas: "Packet Mode Scheduling in Buffered Crossbar (CICQ) Switches", Proc. IEEE Workshop on High Performance Switching and Routing (HPSR 2006), Poznan, Poland, 7-9 June 2006, pp. 105-112, ISBN 0-7803-9570-0; http://archvlsi.ics.forth.gr/bufxbar/

[ChKa06h] N. Chrysos, M. Katevenis: "Preventing Buffer-Credit Accumulations in Switches with Shared Small Output Queues", Proc. IEEE Workshop on High Performance Switching and Routing (HPSR 2006), Poznan, Poland, 7-9 June 2006, pp. 409-416, ISBN 0-7803-9570-0; http://archvlsi.ics.forth.gr/bpbenes/

[ChKa06i] N. Chrysos, M. Katevenis: "Scheduling in Non-Blocking Buffered Three-Stage Switching Fabrics", Proc. IEEE Infocom 2006 Conference, Barcelona, Spain, 23-29 Apr. 2006, 13 pages, CDROM paper ID 13_01; http://archvlsi.ics.forth.gr/bpbenes/

[ChKa05] N. Chrysos, M. Katevenis: "Scheduling in Switches with Small Internal Buffers", Proc. IEEE Globecom 2005 Conference, St. Louis, MO, USA, 28 Nov. - 2 Dec. 2005, 6 pages, CDROM paper ID gc21_3; http://archvlsi.ics.forth.gr/bpbenes/

[KaPa05] M. Katevenis, G. Passas: "Variable-Size Multipacket Segments in Buffered Crossbar (CICQ) Architectures", Proc. IEEE International Conference on Communications (ICC 2005), Seoul, Korea, 16-20 May 2005, CR-ROM paper ID "09GC08-4", 6 pages; http://archvlsi.ics.forth.gr/bufxbar/

[SaKa05] G. Sapountzis, M. Katevenis: "Benes Switching Fabrics with O(N)-Complexity Internal Backpressure", IEEE Communications Magazine (special theme on "Next Generation Switching and Routing"), vol. 43, no. 1, January 2005, pp. 88-94; http://archvlsi.ics.forth.gr/bpbenes/

[ChKa04] N. Chrysos, M. Katevenis: "Multiple Priorities in a Two-Lane Buffered Crossbar", Proc. IEEE Globecom 2004 Conference, Dallas, TX, USA, 29 Nov. - 4 Dec. 2004, CR-ROM paper ID "GE15-3", 7 pages; http://archvlsi.ics.forth.gr/bufxbar/

[Kate04] M. Katevenis, G. Passas, D. Simos, I. Papaefstathiou, N. Chrysos: "Variable Packet Size Buffered Crossbar (CICQ) Switches", Proc. IEEE International Conference on Communications (ICC 2004), Paris, France, June 2004, vol. 2, pp. 1090-1096; http://archvlsi.ics.forth.gr/bufxbar/

[ChKa03] N. Chrysos, M. Katevenis: "Weighted Fairness in Buffered Crossbar Scheduling", Proc. IEEE Workshop on High Performance Switching and Routing (HPSR 2003), Torino, Italy, June 2003, pp. 17-22; http://archvlsi.ics.forth.gr/bufxbar/bxb_scheduling.html

[SaKa03] G. Sapountzis, M. Katevenis: "Benes Switching Fabrics with O(N)-Complexity Internal Backpressure", Proc. IEEE Workshop on High Performance Switching and Routing (HPSR 2003), Torino, Italy, June 2003, pp. 11-16; similar to [SaKa05]; http://archvlsi.ics.forth.gr/bpbenes/

[Kate01] M. Katevenis, Iakovos Mavroidis, G. Sapountzis, E. Kalyvianaki, Ioannis Mavroidis, G. Glykopoulos: "Wormhole IP over (Connectionless) ATM", IEEE/ACM Transactions on Networking, vol. 9, no. 5, October 2001, pp. 650-661; http://archvlsi.ics.forth.gr/wormholeIP/

[IoKa01] A. Ioannou, M. Katevenis: "Pipelined Heap (Priority Queue) Management for Advanced Scheduling in High Speed Networks", Proc. IEEE Int. Conf. on Communications (ICC'2001), Helsinki, Finland, June 2001, pp. 2043-2047; available at: http://archvlsi.ics.forth.gr/muqpro/heapMgt.html

[NiKa01] A. Nikologiannis, M. Katevenis: "Efficient Per-Flow Queueing in DRAM at OC-192 Line Rate using Out-of-Order Execution Techniques", Proc. IEEE Int. Conf. on Communications (ICC'2001), Helsinki, Finland, June 2001, pp. 2048-2052; available at: http://archvlsi.ics.forth.gr/muqpro/queueMgt.html

[KaSM97] M. Katevenis, D. Serpanos, E. Markatos: ``Multi-Queue Management and Scheduling for Improved QoS in Communication Networks'', Proceedings of EMMSEC'97 (European Multimedia Microprocessor Systems and Electronic Commerce Conference), Florence, Italy, Nov. 1997, pp. 906-913; available at: http://archvlsi.ics.forth.gr/muqpro/classSch.html

[Kate97h] M. Katevenis: ``Buffer Requirements of Credit-Based Flow Control when a Minimum Draining Rate is Guaranteed'', Proceedings of HPCS'97 (4th IEEE Workshop on Arch. & Impl. of High Perf. Commun. Subsystems), Chalkidiki, Greece, June 1997; available at: ftp://ftp.ics.forth.gr/tech-reports/1997/1997.HPCS97.drain_cr_buf.ps.gz

[KaSC91] M. Katevenis, S. Sidiropoulos, C. Courcoubetis: ``Weighted Round-Robin Cell Multiplexing in a General-Purpose ATM Switch Chip'', IEEE Journal on Selected Areas in Communications, Vol. SAC-9, No. 8, October 1991, pp. 1265-1279.

[Kate87j] M. Katevenis: ``Fast Switching and Fair Control of Congested Flow in Broad-Band Networks'', IEEE Journal on Selected Areas in Communications, Vol. SAC-5, No. 8, October 1987, pp. 1315-1326.

ATLAS I: a 10 Gbps Single-Chip ATM Switch with Backpressure:

[Korn99b] G. Kornaros, D. Pnevmatikatos, D. Mavroidis, P. Vatsolaki, G. Kalokerinos, C. Xanthaki, G. Dimitriadis, D. Serpanos, M. Katevenis: ``On Optimizing ATLAS I, a 10 Gbps ATM Switch'', Proc. 7th Panhellenic Informatics Conference, Ioannina, Greece, August 1999. Also in Advances in Informatics, Fotiadis/Nikolopoulos Eds, World Scientific Publishing Co, ISBN 981-02-4192-5, pp. 164-177.

[Korn99a] G. Kornaros, D. Pnevmatikatos, P. Vatsolaki, G. Kalokerinos, C. Xanthaki, D. Mavroidis, D. Serpanos, M. Katevenis: ``ATLAS I: Implementing a Single-Chip ATM Switch with Backpressure'', IEEE Micro, vol. 19, no. 1, Jan/Feb. 1999, pp. 30-41.

[Korn98] G. Kornaros, D. Pnevmatikatos, P. Vatsolaki, G. Kalokerinos, C. Xanthaki, D. Mavroidis, D. Serpanos, M. Katevenis: ``Implementation of ATLAS I: a Single-Chip ATM Switch with Backpressure'', Proc. IEEE Hot Interconnects 6 Symposium, Stanford, California, USA, 13-15 August 1998, pp. 85-96; http://archvlsi.ics.forth.gr/atlasI/hoti98/

[KaSD98] M. Katevenis, D. Serpanos, G. Dimitriadis: ``ATLAS I: A Single-Chip, Gigabit ATM Switch with HIC/HS Links and Multi-Lane Back-Pressure'', Microprocessors and Microsystems, special issue on IEEE Std. 1355, Elsevier, March 1998.

[SeKS98] D. Serpanos, M. Katevenis, E. Spyridakis: ``ATLAS I: Building Block for ATM Networks with Credit-based Flow Control'', IEICE Trans. on Communications, Special Issue on ATM Switching Systems for future B-ISDN, Dr. Yamanaka (Editor), Japan, 1998.

[KaSS98] M. Katevenis, D. Serpanos, E. Spyridakis: ``Credit-Flow-Controlled ATM for MP Interconnection: the ATLAS I Single-Chip ATM Switch'', Proceedings of HPCA-4 (4th IEEE Int. Symposium on High-Performance Computer Architecture), Las Vegas, NV USA, Feb. 1998, IEEE Computer Soc. Press, ISBN 0-8186-8323-6, pp. 47-56; available on-line at http://archvlsi.ics.forth.gr/atlasI/, in Postscript (230 KBytes), or gzip'ed Postscript (58 KBytes).

[KaSS97] M. Katevenis, D. Serpanos, E. Spyridakis: ``Switching Fabrics with Internal Backpressure using the ATLAS I Single-Chip ATM Switch'', Proceedings of the IEEE GLOBECOM'97 Conference, Phoenix, AZ USA, Nov. 1997, pp. 242-246; available on-line at http://archvlsi.ics.forth.gr/atlasI/, in Postscript (230 KBytes), or gzip'ed Postscript (53 KBytes).

[Korn97] G. Kornaros, C. Kozyrakis, P. Vatsolaki, M. Katevenis: ``Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow Control'', Proceedings of ARVLSI'97 (17th Conference on Advanced Research in VLSI) Univ. of Michigan at Ann Arbor, MI USA, Sept. 1997, IEEE Computer Soc. Press, ISBN 0-8186-7913-1, pp. 127-144; http://archvlsi.ics.forth.gr/muqpro/queueMgt.html

[SeKS97] D. Serpanos, M. Katevenis, E. Spyridakis: ``ATLAS I: Building Block for ATM Networks with Credit-Based Flow Control'', Proceedings of HPCS'97 (4th IEEE Workshop on Arch. & Impl. of High Perf. Commun. Subsystems), Chalkidiki, Greece, June 1997.

[KVSM97] M. Katevenis, P. Vatsolaki, D. Serpanos, E. Markatos: ``ATLAS I: A Single-Chip ATM Switch for NOWs'', Proceedings of CANPC'97 (Workshop on Communication and Architectural Support for Network-Based Parallel Computing) San Antonio, TX USA, Feb. 1997, Lecture Notes in Computer Science 1199, Springer-Verlag, pp.88-101. ftp://ftp.ics.forth.gr/tech-reports/1997/1997.CANPC97.ATLAS.ps.gz

[KaVa96] M. Katevenis, P. Vatsolaki: ``ATLAS I: A Single-Chip ATM Switch with HIC Links and Multi-Lane Back-Pressure'', EMSYS 96 Conference (ESPRIT OMI 6th Annual Conference: Embedded Microprocessor Systems), Berlin, Germany, Sep. 1996, IOS Press, ISBN 90-5199-300-5, pp. 126-136; http://archvlsi.ics.forth.gr/atlasI/atlasI_emsys96.ps.gz

[KaSV96] M. Katevenis, D. Serpanos, P. Vatsolaki: ``ATLAS I: A General-Purpose, Single-Chip ATM Switch with Credit-Based Flow Control'', Proc. of the IEEE Hot Interconnects IV Symposium, Stanford Univ., CA, USA, Aug. 1996, pp. 63-73; http://archvlsi.ics.forth.gr/atlasI/atlasI_hoti96.ps.gz

[KaVC96] M. Katevenis, P. Vatsolaki, V. Chalkiadakis: ``Credit-Flow-Controlled ATM over HIC Links in the ASICCOM "ATLAS I" Single-Chip Switch'', Real-Time Magazine, vol. 96, no. 3, July 1996, pp. 65-72. ftp://ftp.ics.forth.gr/tech-reports/1996/1996.RTMagazine.ATLAS_I_ATMswitchChip.ps.gz

High-Speed Switching:

[KaVE95] M. Katevenis, P. Vatsolaki, A. Efthymiou: ``Pipelined Memory Shared Buffer for VLSI Switches'', Proceedings of the ACM SIGCOMM '95 Conference, Cambridge, MA USA, 30 August - 1 Sep. 1995, pp. 39-48; http://archvlsi.ics.forth.gr/sw_arch/pipeMem.html.

[KVES95] M. Katevenis, P. Vatsolaki, A. Efthymiou, M. Stratakis: ``VC-level Flow Control and Shared Buffering in the Telegraphos Switch'', Proceedings of the IEEE Hot Interconnects III Symposium, Stanford Univ., CA, USA, Aug. 1995; ftp://ftp.ics.forth.gr/tech-reports/1995/1995.HOTI.VCflowCtrlTeleSwitch.ps.gz.

[Kate94p] M. Katevenis: ``A High-Throughput Data Buffer'', Foundation for Research & Technology -- Hellas (FORTH), Heraklion Crete Greece; USA Patent Number 5,774,653, 30 June 1998; European Patent Application No. 95410074.9, 27 July 1995; Greek Patent Application No. 940100383, 2 Aug. 1994; http://archvlsi.ics.forth.gr/sw_arch/pipeMem.html.

[Kate92] M. Katevenis, G. Kalokerinos, P. Vatsolaki, E. Neonakis, M. Stratakis: ``Internal Organizations of One-Cycle-Latency Crossbar Switch Chips'', ESPRIT P6253 ``SHIPS'' Confidential Working Document, version 1.3, ICS-FORTH, Heraklion, Crete, 31 Dec. 1992.
(Design and evaluation --at the gate netlist level, verified by simulation in Verilog-- of three different organizations for the switch chip --in ECL gate-array technology, with 4 ns cycle time-- for processor to memory interconnection in a parallel supercomputer).

[Kate88] M. Katevenis: ``The Autonet Switch: Architecture & Register-Transfer-Level Design'', Internal Memo, DEC Systems Research Center, Palo Alto, CA, USA, 40 pages, Jan. 1988.
(This was the preliminary switch design for ``Autonet'' -- a high-speed, self-configuring LAN using point-to-point links, precursor of DEC's ``ATM GigaSwitch'').

[Kate87s] M. Katevenis: ``Draft Ideas for a Backplane Superbus'', Memo to the IEEE ``Superbus'' (later ``SCI'') Committee, California, USA, 17 pages, 10 December 1987.
(The IEEE ``Superbus'' Study Group was formed in 1987 in order to standardize a backplane bus in the 1 GByte/s throughput range. This was the first proposal to the group to base the new standard on a ring of point-to-point connections rather than a bus. The Study Group later adopted this idea, renamed the project ``Scalable Coherent Interface'' (SCI), and developed ANSI/IEEE Standard 1596 (1992), which is based on rings of point-to-point connections).

[KaBl85] M. Katevenis, M. Blatt: ``Switch Design for Soft-Configurable WSI Systems'', Proceedings, Conference on Advanced Research in VLSI (ARVLSI), Univ. of North Carolina, Chapel Hill, May 1985. Also published with a small update in: Proceedings of the IFIP WG 10.5 Workshop on Wafer Scale Integration, Grenoble, France, March 1986; Saucier, Trilhe, Eds, North Holland Co, ISBN 0-444-70103-6, pp. 255-270.

Networks of Workstations, Parallel and Distributed Systems:

[Kate99] M. Katevenis, E. Markatos, P. Vatsolaki, C. Xanthaki: "The Remote Enqueue Operation on Networks of Workstations", Informatica - an International Journal of Computing and Informatics, 23(1), pp. 29-39, April 1999, ISSN 0350-5596.

[MaKV98] E. Markatos, M. Katevenis, P. Vatsolaki: ``The Remote Enqueue Operation on Networks of Workstations'', Proceedings of CANPC'98 (Workshop on Communication and Architectural Support for Network-Based Parallel Computing) Las Vegas, NV USA, 31 Jan. 1998, Lecture Notes in Computer Science 1362, Springer-Verlag, pp. 1-14; ftp://ftp.ics.forth.gr/tech-reports/1998/1998.CANPC98.REQ.ps.gz

[KMKD97] M. Katevenis, E. Markatos, G. Kalokerinos, A. Dollas: ``Telegraphos: A Substrate for High Performance Computing on Workstation Clusters'', Journal of Parallel and Distributed Computing (JPDC), vol. 43, no. 2, Academic Press, June 1997, pp. 94-108.

[MaKV97] E. Markatos, M. Katevenis, P. Vatsolaki: ``Notification of Message Arrival in a Parallel Computer System'', Foundation for Research & Technology -- Hellas (FORTH), Heraklion Crete Greece, European Patent Application No. 97410036.4-2201, 19 Mar. 1997.

[MaKa97] E. Markatos, M. Katevenis: ``User-Level DMA without Operating System Kernel Modification'', Proceedings of HPCA-3 (3rd IEEE Int. Symposium on High-Performance Computer Architecture), San Antonio, TX USA, Feb. 1997, pp. 322-331; ftp://ftp.ics.forth.gr/tech-reports/1997/1997.HPCA97.user_level_dma.ps.gz

[MaKa96] E. Markatos, M. Katevenis: ``Telegraphos: High-Performance Networking for Parallel Processing on Workstation Clusters'', Proceedings of HPCA-2 (2nd IEEE Int. Symposium on High-Performance Computer Architecture), San Jose, CA USA, February 1996, pp.144-153; ftp://ftp.ics.forth.gr/tech-reports/1996/1996.HPCA96.Telegraphos.ps.gz

[Vats95] P. Vatsolaki, G. Kalokerinos, M. Stratakis, Ch. Xanthaki, M. Ligerakis, G. Kornaros, A. Dollas, G. Papadourakis, M. Katevenis: ``The Implementation of Telegraphos: a High Speed Communication Architecture'' (In Greek), Proceedings of the 5th Panhellenic Informatics Conference, Athens Greece, December 1995.

[MKKS95] E. Markatos, M. Katevenis, G. Kalokerinos, D. Serpanos: ``An Efficient Processor-Network Interface for Local Area Multiprocessors'', Proceedings of the 4th Int. Workshop on SCI-based High-Performance Low-Cost Computing, SCIzzL, Crete Greece, 3 October 1995, pp. 23-32.

[GoKa93] J. Goodman, M. Katevenis: ``A High-Speed Multiprocessor Network for Delivering Requests to Memory in Processor Time-Stamp Order'' (method for achieving sequential consistency), ESPRIT P6253 ``SHIPS'' Confidential Document, summer 1993.

[VaKa92] P. Vatsolaki, M. Katevenis: ``Implementation of the Memory Barrier in Multi-Stage Processor-Memory Networks'', ESPRIT P6253 ``SHIPS'' Confidential Working Document, version 1.0, ICS-FORTH, Heraklion, Crete, 29 Dec. 1992.
(Innovative design for the method to implement the memory barrier operation in the processor to memory interconnection network of a parallel supercomputer).

Reduced Instruction Set Computer (RISC) Architectures:

[Kate95] M. Katevenis: ``RISC Architectures'', Chapter 20 in Parallel and Distributed Computing Handbook, A. Zomaya Ed., McGraw-Hill, ISBN 0-07-073020-2, 1995, pp. 594-619.

[Kate90] M. Katevenis: ``The Nature of General-Purpose Computations'', Chapter 2 (pp. 13-34) in the book Reduced Instruction Set Computers, W. Stallings, Editor, IEEE Computer Society Press Tutorial, 2nd Edition, ISBN 0-8186-8943-9, 1990.

[KSPS86] M. Katevenis, C. Sequin, D. Patterson, R. Sherburne: ``RISC: Effective Architectures for VLSI Computers'', Chapter 2 in VLSI Electronics: Microstructure Science - Vol. 14: VLSI Design, N. Einspruch, Editor, Academic Press, ISBN 0-12-234114-7, 1986, pp. 36-77.

[Kate85] M. Katevenis: ``Reduced Instruction Set Computer Architectures for VLSI'', 1984 ACM Doctoral Dissertation Award, MIT Press, ISBN 0-262-11103-9, 1985. (U. C. Berkeley TR CSD-83-141, Oct. 1983). (Out of print; copies of the 222 scanned pages of the TR, in GIF, TIFF, and OCR formats, can be found at ftp://sunsite.berkeley.edu/pub/techreps/CSD-83-141.html).

[SKPS84j] R. Sherburne, M. Katevenis, D. Patterson, C. Sequin: ``A 32-Bit NMOS Microprocessor with a Large Register File'', IEEE Journal of Solid State Circuits (JSSC), October 1984.

[SKPS84i] R. Sherburne, M. Katevenis, D. Patterson, C. Sequin: ``A 32-Bit NMOS Microprocessor with a Large Register File'', Proceedings, 31st IEEE Int. Solid-State Circuits Conference (ISSCC'84), San Francisco, February 1984, THAM 12.1, pp. 168-169.

[SKPS83] R. Sherburne, M. Katevenis, D. Patterson, C. Sequin: ``Local Memory in RISCs'', Proceedings, IEEE Int. Conf. on Computer Design: VLSI in Computers (ICCD '83), New York, Nov. 1983, pp. 149-152.

[KSPS83] M. Katevenis, R. Sherburne, D. Patterson and C. Sequin: ``The RISC II Micro-Architecture'', Proceedings of the IFIP TC10/WG10.5 Int. Conference on Very Large Scale Integration (VLSI '83), Trondheim, Norway, 16-19 Aug. 1983, North Holland Pub. Co., pp.349-359. Also published in the Journal of VLSI and Computer Systems, Computer Science Press Inc., Vol. 1, No. 2, 1984.

[SKPS82] R. Sherburne, M. Katevenis, D. Patterson, C. Sequin: ``Datapath Design for RISC'', Proceedings, Conference on Advanced Research in VLSI (ARVLSI), M.I.T., Jan. 1982, pp. 53-62.

[Fitz81] D. Fitzpatrick, J. Foderaro, M. Katevenis, H. Landman, D. Patterson, J. Peek, Z. Peshkess, C. Sequin, R. Sherburne, K. VanDyke: ``VLSI Implementations of a Reduced Instruction Set Computer'', Proceedings of the VLSI Systems and Computations Conference --later called Conference on Advanced Research in VLSI (ARVLSI), Carnegie-Mellon Univ., October 1981, Computer Science Press, pp. 327-336. Also published as: ``A RISCy Approach to VLSI'', VLSI Design Magazine, Vol. II, No. 4, 4th qu. 1981, pp. 14-20. Also published in: Computer Architecture News (ACM SIGARCH), Vol. 10, No. 1, March 1982, pp. 28-32.

[Kate80] M. Katevenis: ``A Proposal for the LSI Implementation of the RISC I CPU (using a 3-phase clock)'', U.C.Berkeley, CS Div., Internal Working Paper, September 1980.
(This internal working paper has served as the specification (block structure and timing) for the VLSI design of the RISC I NMOS single-chip 32-bit processor).