Chip Design Walkthrough (traditional)

FE : logical design

BE : physical design

Bridging

• set of tools

• methodology

RTL design

( technology independent )

Logic Synthesis

(Logic minimization, mapping to technology )

Standard Cell Library

Physical Design

(mostly of cell-based designs)

Statistical wire-load models :

inaccurate for sub-micron technologies, 0.35ìm and smaller

Consideration of design’s physical implementation in Logic Synthesis

Vendors

• Cadence

• Synopsys

• Mentor Graphics

• Teradyne

Previous slide

Next slide

Back to first slide

View graphic version