[photograph of Manolis Katevenis] Univ. of Crete logo

Manolis G.H. Katevenis

Department of Computer Science, University of Crete;

Founder & ex-Head, Computer Architecture and VLSI Systems (CARV) Laboratory,
Institute of Computer Science (ICS),
Foundation for Research & Technology - Hellas (FORTH), Heraklion, Crete, Greece. ICS, FORTH logo

Home Page: https://users.ics.forth.gr/~kateveni/
E-mail: kateveni papaki ics teleia forth teleia gr
Tel: +30 - 2811.39.16.64 (ICS office), +30 - 2810.39.35.64 (CSD office)
Address (Postal and Courier): FORTH-ICS, 100 Plastira Ave, Vassilika Vouton, Heraklion, Crete, GR-70013 GREECE.
UoC-CSD Visiting Address and Office Hours: Room K329, Computer Science Building; usually Mondays and Fridays 11:00 - 11:30 (please call or email before coming, for confirmation and appointment).
FORTH-ICS Visiting Address: Room AA282, East Campus, ICS, FORTH (more local and travel info, from HiPEAC'11). HiPEAC NoE logo

Areas of Interest:
Computer Architecture: Scalable Manycore / Multiprocessor / Warehouse-Scale System Architecture for High Performance Computing (HPC) and Big Data; Exascale Computing; RISC-V;
Interprocessor Communication: Memory-to-memory communication and synchronization – remote-DMA, remote-enqueue; Lean, low-latency Network Interfaces;
Interconnection Network Architecture;
VLSI Systems.

  • Founding member of the European Network of Excellence (NoE) on High-Perfomance and Embedded Architecture and Compilation (HiPEAC) RISC-V logo
  • Member of Academia Europaea – The Academy of Europe (see also www.AE-Info.org for more information of general interest)
  • Stelios Pichoridis Award for Outstanding University Teaching – jointly with Charalampos Katerinopoulos – University of Crete, 2015: Lecture Slides [PDF] [and a TV conference at TV Creta]
  • Award by the Secretary General of the Region of Crete, 2003 – jointly with Stelios Orphanoudakis and Panos Constantopoulos – as the Principal Organizers of the Department of Computer Science, University of Crete.
  • ACM Doctoral Dissertation Award 1984 "For his dissertation Reduced Instruction Set Computer (RISC) Architectures for VLSI."
                – Full text of the Dissertation available on-line
                – In 2015, the RISC Project was recognized as an IEEE Milestone.
                – The RISC-V free and open standard Instruction Set Architecture is an evolution of that project. RISC-II photo

  • Detailed Curriculum Vitae (HTML version of July 2021) [or PDF version]; includes Biography and full lists of: publications, grants, conference organization, invited lectures, students, and courses
  • Brief Biography (2013) (or Greek version (2013)) (or very short version (2012)).
  • Older (March 2011) list of Publications by topic, with pointers to the corresponding project pages.

    Research Projects:



    © Copyright 1998-2023 Manolis Katevenis. Last updated: July 2023.